Device having a cache memory
US10049052B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2014 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Oct 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.