Controller-PHY connection using intra-chip SerDes
US10049067B2 · kind B2 · utility
1Cited by
3References
30Claims
0Family size
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Key dates
| Filing date | Dec 1, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | May 2, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.