Partially molded direct chip attach package structures for connectivity module solutions
US10049961B1 · kind B1 · utility
7Cited by
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24Claims
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Key dates
| Filing date | Mar 30, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Mar 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.