Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit
US10049991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | May 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.