Patent · US Active

Ternary PUF unit and circuit realized by CNFET

US10049992B2 · kind B2 · utility

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1References

2Claims

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Assignee

Ningbo University · CN

Inventors

Pengjun Wang · Zhejiang, CN
Daohui Gong · Ningbo City, CN
Huihong Zhang · Zhejiang, CN
Yaopeng Kang · Zhejiang, CN

Key dates

Filing date	Aug 27, 2017
Grant date	Aug 14, 2018
Priority date	—
Expiry date	Aug 27, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10K19/10
WIPO fieldControl
WIPO sectorInstruments

Abstract

The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column decoder, a ternary output circuit and a ternary PUF unit array; the said ternary PUF circuit is arranged into a 3n rows×3n columns matrix formed by 3n×3n ternary PUF units; the ternary PUF unit comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor and a 10th CNFET transistor; its advantage lies in the fact that it is provided with small circuit area and higher randomness and uniqueness while ensuring proper logic function.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.