Managing parasitic capacitance and voltage handling of stacked radio frequency devices
US10050002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2014 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Nov 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.