Packaged semiconductor devices and packaging methods
US10050013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2015 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06555
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.