Method and circuit for integrated circuit body biasing
US10050037B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 31, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.