Gate structure for semiconductor device
US10050149B1 · kind B1 · utility
12Cited by
21References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | May 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.