Resistive memory element
US10050156B1 · kind B1 · utility
1Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Aug 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory element includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. When a bias voltage higher than a reset voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a reset state. When the bias voltage lower than a set voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a set state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.