Reset management circuit and method therefor
US10050618B1 · kind B1 · utility
1Cited by
4References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Apr 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal management circuit includes a first input terminal to receive a first signal. A first logic portion is coupled to the first input terminal and configured to provide a first output signal. A second logic portion is coupled to receive a second signal and configured to provide a second output signal. The second signal is based on the first output signal and the first signal. An output terminal is coupled to provide a third output signal based on the first output signal and the second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.