Quantization noise cancellation for fractional-N phased-locked loop
US10050634B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.