Partially asynchronous clock scheme for SAR ADC
US10050639B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Nov 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for controlling an SAR ADC by generating a first signal to control sampling of an analog input voltage at a DAC, and then generating a second signal to start a successive approximation sequence at a comparator and SAR engine to convert the analog input voltage to an N-bit digital value, where the successive approximation sequence includes a settling phase for each bit of the N-bit digital value and is controlled to synchronously end in response to a first synchronous clock signal, and also includes a comparison phase for each bit of the N-bit digital value to allow for comparison of the analog input voltage to a reference voltage, where each comparison phase is controlled to synchronously start in response to the first synchronous clock signal and asynchronously end in response to a second asynchronous clock signal that is self-generated by the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.