Low power scheme for bit flipping low density parity check decoder
US10050642B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Mar 17, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Mar 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3715
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the determined syndrome weight to set an optimal clock frequency for the LDPC decoding. The LDPC decoder applies hard decision decoding using a bit-flipping algorithm. When it is determined that the syndrome weights begin to overlap, the method further includes: performing one more iteration in hard decision hard decoding mode; providing a power boost to the LDPC decoder; and switching to hard decision soft decoding mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.