Method of reducing latency in a flexible parser and an apparatus thereof
US10050833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2014 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Jun 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether parsing for this packet is completed and, thus, no further processing is required by subsequent parser engines. Each parser engine also includes a counter, which is incremented whenever a packet enters the parser engine and is decremented whenever a packet exists the parser engine. A packet bypasses the parser engine based on the counter of the parser engine and the status information of that packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.