Stacked image sensor pixel cell with in-pixel vertical channel transfer transistor and reflective structure
US10051218B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | May 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
Abstract
A pixel cell has a photodiode, a readout circuit, a vertical transfer transistor and a reflective structure. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry. The reflective structure is positioned between the readout circuit and the photodiode to reflect incident light, that passes through the photodiode without being absorbed, back towards the photodiode for a second chance at being absorbed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.