Patent · US Active

Integrated system and method for testing system timing margin

US10054635B2 · kind B2 · utility

3Cited by
4References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 9, 2016
Grant dateAug 21, 2018
Priority date—
Expiry dateJul 24, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/16
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A built-in test circuit for testing a system timing margin of a processing device under-test is provided. The processing device includes a controller and first clock circuit, wherein the first clock circuit generates a first clock signal and the first clock signal is a main clock signal provided for operation of the processing device. The built-in test circuit includes a second clock circuit and a logic circuit, both of which are integrated with the processing device. The second clock circuit generates a second clock signal. The logic circuit processes the first and second clock signals and outputs a third clock signal. The third clock signal is used to determine system timing margin of the processing device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.