Memory storage windows in a memory system
US10055343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Dec 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a first plurality of addressable memory locations associated with a first data storage window and a second plurality of addressable memory locations associated with a second data storage window. The memory device includes a controller that receives requests from a host device to identify the first data storage window and the second data storage window. The controller receives requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window. The controller receives memory commands from the host device that indicate the first window index value and at least one address. The controller accesses, based at least on the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.