Systems and methods for coalescing interrupts
US10055369B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Mar 27, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for coalescing interrupts temporally for later processing are described. An interrupt controller in a computing system maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.