Orthogonal differential vector signaling codes with embedded clock
US10055372B2 · kind B2 · utility
83Cited by
273References
20Claims
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Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Aug 23, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.