Automated checker generation

US10055522B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Joerg Behrend · Rangendingen, DE
• Holger Horbach · Aidlingen, DE
• Alexander Jung · Kleinkahl, DE
• Klaus Keuerleber · Stuttgart, DE
• Daniel Sentler · Passau, DE
• Jurgen Wakunda · Ilsfeld, DE

Key dates

• Filing date: Jun 6, 2016
• Grant date: Aug 21, 2018
• Expiry date: Sep 30, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3308
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfill the requirements specified in the matching strategy.