Patent · US Active

Ternary 2-9 line address decoder realized by CNFET

US10056134B2 · kind B2 · utility

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1References

8Claims

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Assignee

Ningbo University · CN

Inventors

Pengjun Wang · Zhejiang, CN
Daohui Gong · Ningbo City, CN
Yuejun Zhang · Zhejiang, CN
Yaopeng Kang · Zhejiang, CN

Key dates

Filing date	Aug 28, 2017
Grant date	Aug 21, 2018
Priority date	—
Expiry date	Aug 28, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor, a 10th CNFET transistor and an 11th CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.