Duty cycle adjustment circuit
US10056891B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2018 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Feb 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle adjustment circuit includes: a delay circuit to delay an input clock signal to produce a delayed clock signal having a rising edge partially overlapping the rising edge of the input clock signal, the input clock signal oscillating between first and second values about a midpoint value; a blender circuit to blend the input clock signal and the delayed clock signal to produce a blended clock signal; a buffer circuit to buffer the input clock signal for an amount of time comparable to the blender circuit, to produce a buffered clock signal; and a combiner circuit to combine the buffered and the blended clock signals to produce an output clock signal that transitions to or remains at the first value when both the buffered and blended clock signals are on the first value side of the midpoint value, and otherwise transitions to or remains at the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.