Continuous coarse-tuned phase locked loop
US10056911B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.