Simultaneous cancellation of multiple spurs from different sources
US10056912B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for phase locked loop (PLL) multiple spur cancellation includes multiple spur cancellation circuits and a number of multiplexers that are coupled to respective input ports of the spur cancellation circuits. The circuit further includes a number of demultiplexers that are coupled to respective output ports of the spur cancellation circuits. Each spur cancellation circuit can cancel a spur associated with a spur source, and input nodes of the multiplexers and output nodes of the demultiplexers are coupled to different connection points of a PLL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.