Data forwarding with speculative error correction
US10057017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Mar 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.