Data handoff between randomized clock domain to fixed clock domain
US10057048B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Sep 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.