Patent · US Active

Pseudo dual port memory

US10061542B2 · kind B2 · utility

2Cited by

2References

14Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Tony Chung Yiu Kwok · San Diego, US
Nishith Desai · Austin, US
Changho Jung · Hwaseong-si, KR

Key dates

Filing date	Sep 15, 2015
Grant date	Aug 28, 2018
Priority date	—
Expiry date	Sep 15, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.