Redundancy elimination in single instruction multiple data/thread (SIMD/T) execution processing
US10061591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2015 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing execution of redundant threads in a processing environment. The method includes detecting threads that include redundant work among many different threads. Multiple threads from the detected threads are grouped into one or more thread clusters based on determining same thread computation results. Execution of all but a particular one thread in each of the one or more thread clusters is suppressed. The particular one thread in each of the one or more thread clusters is executed. Results determined from execution of the particular one thread in each of the one or more thread clusters are broadcasted to other threads in each of the one or more thread clusters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.