MUX select control of two phase shifted data in write precompensation
US10062407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2018 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Jan 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A precompensation circuit can include: a rising edge interpolator circuit configured to generate a phase shifted rising edge data signal; a falling edge interpolator circuit configured to generate a phase shifted falling edge data signal; a multiplexer circuit coupled with the rising edge interpolator circuit and with the falling edge interpolator circuit to multiplex the phase shifted rising edge data signal and the phase shifted falling edge data signal into an output data signal responsive to a select signal; and a control circuit coupled with the select input of the multiplexer circuit to control production of the output data signal, wherein the control circuit is further coupled with both the rising edge interpolator circuit and the falling edge interpolator circuit to change the select signal to the multiplexer circuit at times determined by both the phase shifted rising edge data signal and the phase shifted falling edge data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.