Zero bias fuse cell
US10062448B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Nov 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a fuse cell with a current mirror. The first leg of the current minor includes first and second N-type transistors coupled in series between the upper and lower rails and the second leg includes third and fourth N-type transistors coupled in series between the upper and lower rails. The size of the first N-type transistor is (Y·A1), the second N-type transistor is (X·A2), the third N-type transistor is (X·A1) and the fourth N-type transistor is (Y·A2) where X and Y are integers and A1 and A2 are the sizes of respective reference transistors. A fuse has a first terminal coupled between the first and second N-type transistors and a second terminal coupled between the third and fourth N-type transistors; a first control node on the second leg of the current minor is coupled to control the voltage at an output node of the fuse cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.