Composite bond structure in stacked semiconductor structure
US10062656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2016 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Aug 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/059
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.