Level shift circuit
US10063226B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2018 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Mar 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift circuit including serially-connected first resistor and first transistor and serially-connected second resistor and second transistor, a protection circuit that receives signals at a first junction between the first resistor and the first transistor and a second junction between the second resistor and the second transistor, a latch circuit receiving an output of the protection circuit, serially-connected third and fourth transistors and serially-connected fifth and sixth transistors respectively connected in parallel to the first and second resistors, a switching time detection circuit that receives the signals at the first and second junctions and detects an occurrence of switching noise, and first and second logical AND circuits that receive outputs of the switching time detection circuit and the signals at the first and second junctions, and respectively control the fourth and sixth transistors. The third and fifth transistors are controlled by an output, or an inversion thereof, of the latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.