Level shifting circuit
US10063227B2 · kind B2 · utility
2Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Jan 3, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.