TFT array substrate and liquid crystal display panel
US10067389B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Apr 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor (TFT) array substrate includes a plurality of data lines, at least one first common electrode, and at least one resistance reduction structure. The resistance reduction structure is connected to the first common electrodes and located corresponding to one of the data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.