Multi-phase clock method and circuit for dynamic power control in a data processing pipeline
US10067550B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Oct 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B5/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.