Execution of divergent threads using a convergence barrier

US10067768B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Gregory Diamos · San Jose, US
• Richard Craig Johnson · Elkton, US
• Vinod Grover · Mercer Island, US
• Olivier Giroux · Santa Clara, US
• Jack Choquette · Palo Alto, US
• Michael A. Fetterman · Boxborough, US
• Ajay Sudarshan Tirumala · Cupertino, US
• Peter Nelson · San Francisco, US
• Ronny Meir Krashinsky · San Francisco, US

Key dates

• Filing date: Jul 13, 2015
• Grant date: Sep 4, 2018
• Expiry date: May 16, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/38885
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method, system, and computer program product for executing divergent threads using a convergence barrier are disclosed. A first instruction in a program is executed by a plurality of threads, where the first instruction, when executed by a particular thread, indicates to a scheduler unit that the thread participates in a convergence barrier. A first path through the program is executed by a first divergent portion of the participating threads and a second path through the program is executed by a second divergent portion of the participating threads. The first divergent portion of the participating threads executes a second instruction in the program and transitions to a blocked state at the convergence barrier. The scheduler unit determines that all of the participating threads are synchronized at the convergence barrier and the convergence barrier is cleared.