Time-based on-chip hardware performance monitor
US10067847B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2015 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a performance monitor for a functional block of a system, the performance monitor comprising a counter circuit, wherein the counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter coupled to the time window counter. The event counter is configured to count a number of occurrences of an event occurring in the functional block during the counting period, and record the number of occurrences of the event during the counting period and generate an output trigger signal when the number of occurrences of the event during the counting period is outside of a programmable threshold band, or after receiving an input trigger signal from a cross trigger network triggered by other performance monitors in electrical communication with the cross trigger network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.