Patent · US Active

Microcontroller or microprocessor with dual mode interrupt

US10067892B2 · kind B2 · utility

0Cited by
3References
31Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 3, 2016
Grant dateSep 4, 2018
Priority date
Expiry dateSep 2, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F13/24
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.