Apparatuses and methods for accessing and scheduling between a plurality of row buffers
US10068636B2 · kind B2 · utility
2Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Dec 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a dynamic random access memory (DRAM) array, which comprises a plurality of bit lines connectable, respectively, to at least two row buffers of the DRAM array. The two row buffers are respectively connectable to data input/output (I/O) lines and are configured to electrically connect the two row buffers to the bit lines and data I/O lines in a mutually exclusive manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.