Semiconductor device and manufacturing method thereof
US10068774B2 · kind B2 · utility
1Cited by
18References
20Claims
0Family size
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Key dates
| Filing date | Dec 1, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Dec 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1−xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1−yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1−zGez is formed on the second epitaxial layer. Z is smaller than y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.