Semiconductor package
US10068817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Mar 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and die assembly with a package having an exterior surface and an interior space, the interior space defined by a first side wall, and a second side wall that opposes the first side wall. Also part of the assembly is a package floor and a package ceiling. The package floor includes package floor conductors. The package ceiling opposes the package floor and includes package ceiling conductors in the package ceiling. One or more semiconductor dies are on the floor of the package floor. Electrical conductors electrically connect the one or more floor dies to the package floor conductors. One or more semiconductor dies are located on the package ceiling. Electrical conductors are configured to electrically connect the one or more ceiling dies to the package ceiling conductors. An air space is located between the package floor and the package ceiling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.