Enhancement mode field-effect transistor with a gate dielectric layer recessed on a composite barrier layer for high static performance
US10068976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.