Pulsed decision feedback equalization circuit
US10069658B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2015 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Sep 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/72
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.