Intra prediction processor with reduced cost block partitioning and refined intra mode selection
US10070128B2 · kind B2 · utility
9Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | May 4, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/96
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hardware processor has a per block size intra mode processor to perform intra mode searches for best intra modes for different block sizes. A cost processor computes cost values for the different block sizes, where the cost values are based upon at least one of a simplified distortion estimate or a simplified bit rate estimate. A selective block merger processor establishes a final partition of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.