Scalable and parameterized VLSI architecture for compressive sensing sparse approximation

US10073701B2 · kind B2 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Dejan Markovic · Los Angeles, US
• Fengbo Ren · Tempe, US

Key dates

• Filing date: Jul 29, 2014
• Grant date: Sep 11, 2018
• Expiry date: Feb 13, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G16H40/63
• WIPO field: Medical technology
• WIPO sector: Instruments

Abstract

Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.