Patent · US Active

Last branch record indicators for transactional memory

US10073719B2 · kind B2 · utility

1Cited by

2References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ravi Rajwar · Portland, US
Peter Lachner · Heroldstatt, DE
Laura A. Knauth · Portland, US
Konrad K. Lai · Beaverton, US

Key dates

Filing date	Apr 18, 2016
Grant date	Sep 11, 2018
Priority date	—
Expiry date	Jun 24, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/3636
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.