Flash memory read error recovery with soft-decision decode
US10073734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2015 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Feb 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/41
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.