Receiver circuit and operating method of the same
US10074339B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2015 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Aug 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes a CLK_LP circuit, a CLK_HS circuit, a DATA_LP circuit, a DATA_HS circuit and a malfunction detection circuit. The CLK_LP circuit and the CLK_HS circuit are connected to the clock lane. The DATA_LP circuit and the DATA_HS circuit are connected to the data lane. The malfunction detection circuit is configured to assert an HS-mode return signal when a first mode signal indicating the communication mode of the clock lane is set to the LP mode at a moment when the second mode signal indicating the communication mode of the data lane is switched from the HS mode to the LP mode. The CLK_LP circuit sets the first mode signal to the HS mode in response to the assertion of the HS-mode return signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.