Mode-changeable dual data rate random access memory driver with asymmetric offset and memory interface incorporating the same
US10074411B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.